Architectural Overview

The Grand Interconnect is implemented as a "ring'' architecture with a single host which functions as the controlling node. Refer to Figure . The single master node eliminates contention and arbitration issues associated with conventional peer-to-peer networks. The implementation is based on 125 MHz bit-serial technology. For this architecture a relatively simple protocol can be used which provides a maximum effective data throughput of 10 Mbytes/second for large block transfers. Local buffering at the I/O chassis level facilitates transfer of large data blocks, and the simplified protocol eliminates the need for complex network protocol firmware.

To facilitate the data acquisition process, each node includes a firmware-based "list processor'' that can be triggered to execute a local "scan list'' and acquire data either into a local buffer or respond to a physical I/O request on the serial interconnect in response to a host I/O request. This feature provides a built-in low-latency scatter-gather capability that can respond to I/O chassis events in well under 1 microsecond with a very high degree of determinism. The current implementation of the list processor is based on the Texas Instrumentations TMS320C25 40 MHz DSP. The choice of using a DSP for the list processing element is governed by the low cost, high speed, and flexibility that is achieved through firmware updates. Through use of custom firmware and extensions to the scan list structure it will be possible to meet many applications with special requirements.