Introduction

The Grand Interconnect is a high-throughput, low latency, highly deterministic I/O subsystem designed for high performance distributed data acquisition applications. The interconnect is specifically designed to facilitate synchronous data acquisition over a distributed area while carefully maintaining the time coherency of the data. It operates over a wide range of sampling rates and throughputs as well as collect data from a number of modular standard I/O chassis including VXI, CAMAC (IEEE 583) and VME (IEEE 1014).

This implementation of the interconnect is based on 125 MHz bit-serial technology and a protocol that provides data throughputs to 10 Mbytes/second. For short distances (up to 5m) coaxial cable can be used. For longer distances or where good isolation is required, a fiber optic link is supported. Fiber optic links up to 2 km between nodes are available using 50 or 62.5 micron cable. The interconnect supports up to 126 nodes or I/O chassis.

Each node controller includes a local "scan list" capability that can be triggered by a local internal crystal-controlled programmable clock, an externally supplied TTL trigger, a local I/O chassis interrupt, or by a host generated trigger message. Each node also provides local data buffering.

The interconnect is designed as a single master (host) with up to 126 addressable slave nodes. In general, all communication is initiated by the host except that any node may inject an asynchronous event for the host between messages on the highway. This architecture eliminates much of the overhead associated with conventional peer-to-peer networks. This includes contention for network access as well as providing a method for arbitrating network mastership. This architecture results in a greatly simplified protocol and permits implementation of the link management in hardware logic which results in higher performance and lower latencies than competing alternatives. The ability for a node to inject asynchronous event messages into the serial stream minimizes latencies associated with reporting of asynchronous events at the node level.

One of the features of this architecture is that slave controllers can implement the interconnect protocol in hardware logic due to its simplicity. This feature minimizes node costs since a high performance processor is not needed to support a networking protocol.