Grand Interconnect Architecture--

Synchronization Features

Synchronous deterministic capture of data is an important consideration in a data acquisition system. In any application where it is important to extract the time history of one or more signals requires that the relative sampling time of the signal(s) be known. It generally is not required to time-stamp at high resolution exactly when each sample is taken, but rather to sample at one or more known fixed frequencies and to use the relative position of the data in the data stream to infer the sample time. In such a scenario the data acquisition process must be driven by a stable, known frequency source with minimum jitter--typically a crystal clock.

The Grand Interconnect provides several mechanisms to support synchronous data acquisition. First, the V160 Slot-0 controller includes a precision 10 MHz clock to drive the VXI 10 MHz clock line as well as logic to derive sub-multiples of this clock to drive the list processor and trigger lines. By driving the ADCs and other I/O elements in the slave I/O chassis from these clocks and synchronously triggering the list processor it is possible to acquire and buffer data at multiple rates within the slave I/O chassis in a highly deterministic manner with very low jitter in the sampling interval. For co-located chassis the V160 Slot-0 controller provides a mechanism to share a common 10 MHz clock and one trigger line across multiple chassis to insure synchronous data acquisition across multiple chassis.

V160 needs to provide capability to share a common 10 MHz clock and at lease one trigger line among a group of co-located main frames! One V160 would act as the common 10 MHz clock, and pass the clock (daisy chained) to other main frames in the group-obviously some fan-out scheme would be nice to give less jitter, but would be over-kill in most applications. The V207/V208 and other "triggerable'' I/O modules should derive the triggers from the 10 MHz clock so we can synchronize data acquisition across mainframes. The V160 list processor MUST be capable of deriving a submultiple of the 10MHz clock (software programmable) to drive at least one trigger line and the list processor firmware. The V160 must be capable of handling multiple rates. These rates do not need to be independent, but rather sub-multiples of the highest rate. Also it is probably OK if we come up with a scheme that uses a single buffer. The V160 needs to provide a 32-bit (64-bit is better) counter that counts the 10 MHz clock. The counter needs to be readable from the list processor or maybe even the VXI bus as well. The purpose is to provide a "time stamp'' for those who just have to have one.

For highly distributed applications with less stringent jitter requirements, the Grand Interconnect provides a list processor at the host interface that can be triggered either from an internal programmable clock or an external clock. When triggered the host list processor can generate a sequence of interconnect commands that initiate data capture in various slave I/O chassis and initiate transfer to the host.

An associated feature that can be used to better synchronize I/O chassis activity in a distributed configuration is the broadcast trigger message. Each V160 includes a programmable delay that is associated with a broadcast trigger. This delay can be set up to compensate for fixed routing and propagation delays around the interconnect loop. Using this technique, it is possible to achieve somewhat better synchronization of data acquisition activities than otherwise.

For applications that require some form of time stamping of the data, e.g. when data acquisition is triggered from an asynchronous external event, the Slot-0 provides an internal clock. This internal clock can be read as part of the data scan.

Error Detection