KineticSystems ::. Data Acquisition (DAQ)

Technical Notes

V200 Simultaneous and Synchronous Sampling

I. INTRODUCTION

Due to the architecture of the sigma-delta ADC which uses digital filtering and decimation techniques, the concept of simultaneous sampling loses its literal meaning since any given output sample is a weighted average over some number of input samples. Thus there is no well defined time when the analog signal was "sampled.'' This, however does not preclude the output of two different channels being time or phase related.

Running sigma-delta ADCs from a common clock is sufficient to guarantee a fixed phase relationship between the channels. By also resetting the ADCs from a common reset signal the absolute phase difference between channels can be eliminated.

In most applications the real requirement is either a stable or zero phase relationship between different channels not simultaneous sampling. Simultaneous sampling is only one means to an end that works for conventional ADCs. Obviously sigma-delta ADCs can meet the real requirement.

There are two considerations when attempting to use V200s in applications requiring either synchronous or simultaneous sampling of data.

Synchronous Sampling: For synchronous sampling a common clock is required for all ADCs.
Simultaneous Sampling: For simultaneous sampling in addition to the common clock one must insure that the internal logic in all ADCs start from a common point. In particular that the counters that control the decimation in the internal FIR filters are reset by a common hardware generated signal. Note that the time scale for resetting the internal counters is determined by the oversampling clock which may be as high as 12.8 MHz. This is well beyond the time scale of any software solution.

Prior to attempting to employ the techniques in this technical note it is important that the V200s be at a minimum revision level of rev. 8 on the VXI-211 board and rev. 6 on the VXI-216 board. Earlier versions do not have the necessary features to permit full synchronization. Users with older versions should consult the factory to get their boards updated.

II. V200 CLOCKING

The V200 provides a number of clocking options. The Sigma Delta ADC chip ultimately requires a 64 times oversampling clock. The V200 is capable of selecting one of three sources of the oversampling clock: An internal oversample clock derived by dividing down a 12.8 MHz crystal clock, an oversample clock derived from a phase lock loop (PLL) , or a user supplied external oversample clock via a front-panel SMB . For reasons of clarity the various sources of the oversample clocks will be referred to as crystal oversample clock , PLL oversample clock , and the external oversample clock . The PLL can be driven at the desired sample rate from one of the following sources: An internal sample clock , a VXI trigger line or a front-panel SMB . The PLL generates the oversample clock by multiplying the input clock by 64.

PLL Considerations

The Phase Lock Loop (PLL) is provided as a convenience to the V200 user. In conventional ADCs a clock is provided at the desired conversion rate. With the Sigma-Delta ADC the ADC must be clocked at 64 times the desired "effective'' sample rate. The PLL allows the user to employ a clock at the desired sample rate and the PLL multiplies this clock by a factor of 64 to obtain the PLL oversample clock .

The user needs to be aware that a PLL is a free-running oscillator with a feedback loop that tries to maintain the output frequency at 64 times the input frequency. If the output frequency drifts a little too high the feedback will bring the output frequency down and visa versa. Thus the oversampling clock generated by the PLL will drift slightly around the desired oversample rate. The cause of the drifting is typically due to unavoidable noise in the feedback loop. Since the Sigma-Delta ADC in effect averages samples at the oversampling rate and decimates the resulting data down to the effective sample rate, the effects of PLL "hunting'' should not be a major problem in some applications.

In applications with precise timing requirements it is advisable to use either the internal crystal oversampling clock which provides a limited number of sample rates based on dividing down a 12.8 MHz crystal clock or by providing a suitable external SMB oversampling clock .

III. SYNCHRONEOUS SAMPLING (CONSTANT PHASE)

Some applications require that the phase between different channels remain constant, however a fixed phase difference is acceptable. In such cases it is necessary to run all channels from a common clock. The V200 provides several means to accomplish this. It should be noted that in the V200 the ADCs are broken into two more or less independent groups A and B. Each group can be clocked independently. For this reason synchronization issues apply equally between groups within a V200 as well as between V200s.

Quasi-synchronous Sampling

This method uses the TTL trigger lines to distribute the sample clock to each V200 and the individual PLLs to generate the oversample clock. For the reasons discussed in Section , the phase between channels will vary slightly in time due to the different PLLs. This method only provides a limited degree of synchronization, however it should be sufficient to guarantee that corresponding buffer segments across multiple V200s are ready based on testing the status of a single buffer segment.

PLL-driven Synchronous Sampling

This approach uses one of the V200's PLL as a master oversample clock. The master oversample clock is routed to the clock-in of the next V200 and clock-out to the following V200, etc. Using this technique there will be a small fixed logic delay of the clock between clock-in and clock-out. All channels will however be synchronous with a fixed phase between V200s.

Internal (Crystal) Oversample Clock Synchronous Sampling

This approach uses the internal crystal oversample clock of a master V200 instead of the PLL oversample clock . Otherwise it is identical to Section . The primary restriction with this approach is the limited selection of clock frequencies.

External Oversample Clock Synchronous Sampling

This approach is essentially the same as Section , however the oversample clock is derived from an external source to the first V200 rather than the PLL.

IV. BUFFER SYNCHRONIZATION

Synchronization of data samples across multiple V200s or different groups within a V200 can be important in many applications. In general the ADCs in the V200 run continuously to minimize temperature effects whether the data is being captured in the data buffers or simply being discarded. In multiple V200 applications or single V200 applications using both group A and B multi-buffers it is frequently desirable to insure that the data samples from a given relative position in different buffers represent the analog input at roughly the same time, typically within the period of the effective sampling rate.

Due to the high sampling rates of the V200 it is not possible for the software to setup multiple V200 groups and start them within a clock period. To accomplish this level of synchronization it is necessary to setup and "arm'' each of the V200s, and then start them storing data from a common hardware trigger. For the V200 the hardware trigger is a selected VXI trigger line.

V200 Buffer Synchronization Procedure

The following procedure should be followed to synchronize data buffers across multiple V200s as well as between groups A and B within a V200.

Step 1: Issue the following commands to each V200 Group A and/or B that are to be synchronized:

Set CLR MBF (bit 9) in the Multibuffer Control Registers Group A (0x30) and/or Group B (0x50) . Resets Multibuffer pointers.
Issue OP-code '0x1C' to Group A DSP. Synchronizes Group A and B in each V200.
Set ASR ENA (bit 19) and selected trigger line (bits 16-18) in the Trigger Reception Registers Group A (0x0C) and/or Group B (0x10) . Selects trigger line which will start data collection and enables arming of run mode.
Issue OP-code '0x281' to each Group DSP being synchronized. Arms run mode pending selected trigger.

Step 2: Generate trigger on designated trigger line to start data acquisition.

Following execution of the above procedure buffer pointers will be reset to their initial values. For each succeeding tick of the sample clock a block of data will be transferred to the data buffers for each respective group A and/or B. Data samples within corresponding blocks will represent values sampled within one sample clock interval. For more precise timing requirements refer to Section section .

VI. SIMULTANEOUS SAMPLING (ZERO PHASE)

For applications requiring simultaneous sampling a number of issues become critically important. These include:

The oversampling clocks at the ADCs must have minimum relative delays and be stable.
The internal state of the ADCs must be reset to a common state.
The organization of time sequential data in the respective buffers must be either known or preferably the same.

When the simultaneous sampling procedure discussed below has been followed, data samples within corresponding blocks will have been sampled within approximately PM25 nsec.

Oversampling Clock

Three alternatives are possible. The best is to provide an external oversampling clock and distribute it to each of the SMB Clock-in connectors. In most cases it is satisfactory to simply use SMB Tee connectors to each SMB input from the external clock. If short cables are used the cable delays should not seriously affect timing. Cable delays are approximately 1 nsec/ft. Use of the clock-out SMB to daisy chain the oversample clock is not recommended because of gate delays in the internal circuits.

The second alternative is to use one of the internal crystal oversampling clocks in the V200. It must be routed to the clock-out SMB and daisy-chained to the clock-in of the other V200s as in the first case.

Third alternative is to use a single PLL to generate the PLL oversampling clock . In this case the PLL oversampling clock should be routed to the clock-out SMB on the front panel and distributed to the remaining V200s similar to the external clock above. While there could be some slight variations in oversampling clock frequency it will be identical for all channels. Refer to Section regarding PLL stability.

Simultaneous Sampling Setup Procedure

Setup for simultaneous sampling requires the following steps. Note that there is a slight difference in setup whether using a multibuffer or commport options. In either case it is necessary to execute the full procedure.

Step 1: The first step involves resetting the internal state of the ADC chips. This requires the use of a trigger line to simultaneously reset all ADC chips. For each of the ADC groups that are to be simultaneously sampled perform the following:

Set the SYN ENA bit 23 and the trigger line selection bits 20-22 in the Trigger Reception Register A/B (0x0C / 0x10) .
Issue OP-code '1E' to DSP A or B as appropriate.

All ADCs will be reset by the next trigger edge on the selected trigger line. Step 2: Generate selected trigger defined in Step 1 to reset all ADC chips to a common state. Step 3: Issue the following commands to each V200 Group A and/or B that are to be synchronized:

IF USING MULTIBUFFER: Set CLR MBF (bit 9) in the Multibuffer Control Registers Group A (0x30) and/or Group B (0x50) . Resets Multibuffer pointers.
IF USING COMMPORT: Set the Commport Enable bit in the CSR or Communication Control Port Register.
Set ASR ENA (bit 19) and selected trigger line (bits 16-18) in the Trigger Reception Registers Group A (0x0C) and/or Group B (0x10) . Selects trigger line which will start data collection and enables arming of run mode.
Issue OP-code '0x281' to each Group DSP being synchronized. Arms run mode pending selected trigger.

This procedure re-sets buffer pointers and arms each V200 Group so that the next trigger on the selected trigger line will place all the V200s in the group into the data acquisition mode with data starting in segment 0 of the multi-buffer. Step 4: Issue the following command to a single selected V200 in the synchronized group .

Set SSP-ENA (bit 23) and the selected trigger line (bits 20-22) in the Trigger Source Register Group A (0x04) .

This will cause the selected V200 to generate a trigger on the selected VXI trigger line. The timing of this trigger is determined by the V200 relative to the sample clock such that the data transferred to the V200 buffers represent data sampled within a sample clock interval. Do not use any other trigger source to start data acquisition other than the trigger generated by the SSP ENA of the Trigger Source Register as the trigger timing may not be such as to guarantee that data in all multibuffers are from the same sample clock.